The present invention relates to a PLL circuit applicable to an optical disk or magnetic disk drive apparatus, etc. More particularly, the present invention relates to a PLL circuit for providing an optical response at any time corresponding to the change in reproducing speed in a wide range thereof. The present invention also relates to a PLL circuit for stabilizing a frequency of an output clock signal in a period in which input read data are lost.
A digital information memory apparatus such as an optical disk or magnetic disk drive apparatus, etc., comprises a PLL (Phase-Locked Loop) circuit for producing a clock signal indicating a reproducing timing for reliably extracting read data when information stored in such an apparatus is reproduced.
Such a PLL circuit has filter characteristics in itself. In this circuit, when a band width, a damping factor, etc., are set to suitable values, dynamic responses to the input read data such as lock time, capture range, characteristics for removing jitter, etc., are different from each other.
Namely, when the band width is set to be wide, the lock time and capture range are improved, by tthe jitter removing characteristics deteriorate. When the band width is set to be narrow, the jitter removing characteristics are improved, but the lock time and the capture range are not improved. Further, when the damping factor is set to be high, the lock time and the capture range are improved, but the jitter removing characteristics deteriorate. When the damping factor is set to be low, the jitter removing characteristics are improved, but the lock time and capture range are not improved.
Accordingly, when the band width, damping factor, etc., are set in the above-mentioned PLL circuit, it is necessary to sufficiently consider the reproducing speed of the input read data and the required lock time, etc.
A recording and reproducing system of an optical disk, where the recording and reproducing speed is changed depending on the radius of a track for increasing a memory capacity, is known. In this system, the recording and reproducing speed is increased as the pickup approaches the outer circumference of the disk in order to record data at a constant density irrespective of a track radius thereby increasing the memory capacity per disk surface. In such a system, the recording and reproducing speed is greatly changed depending on the track radius.
Accordingly, it is necessary to change the dynamic characteristics of the above-mentioned PLL circuit corresponding to the reproducing speed. However, since the band width, damping factor, etc., are fixedly set in the conventional PLL circuit, it is impossible to obtain an optimal response corresponding to all the reproducing speeds from the inner circumference to the outer circumference of the disk.
For example, in the conventional PLL circuit in which the band width is set such that the lock time is optimal with respect to the high reproducing speed (which corresponds to a speed on the outer circumferential side of the disk), the jitter removing characteristics are deteriorate with respect to the low reproducing speed (which corresponds to a speed on the inner circumferential side of the disk) so that the data tend to be read in error.
When the band width is set such that the jitter removing characteristics are optimal with respect to the low reproducing speed, the apparent lock time becomes longer with respect to the high reproducing speed and the number of bits corresponding to the lock time amount becomes greater due to the increased reproducing speed although the lock time is the same in the above both cases. Further, since the period for enabling the data to be really read from the starting operation of the PLL circuit becomes long, for example, repetitious patterns, etc., must be recorded irrespective of the information really required in this period, thereby reducing the memory capacity for use.
Further, in another conventional PLL circuit, in the data read period from the disk, when there are certain defects etc. in the disk, the read data are sometimes lost for a long period such as a period corresponding to about several tens to several hundred bits.
In such a situation, output signals of a phase comparator are held in a disabled state so that an electric current flowing through a loop filter for receiving output signals of the phase comparator is held to be zero. Accordingly, when the above-mentioned filter has ideal integral characteristics, an output voltage from the filter is held to be a constant value, thereby constantly holding the frequency of an output clock signal from a voltage-controlled oscillator operated on the basis of the output signal from the loop filter.
However, in the real circuit construction, the output voltage of the loop filter does not become constant even in the above-mentioned state by an input electric current of an operational amplifier constructing the loop filter or a leak electric current flowing through a diode constructing the loop filter, etc. Therefore, the output voltage of the loop filter is changed in accordance with time in a shape in which the value of the input bias electric current is integrated for example.
Accordingly, even in the read data losing period, the frequency of the output clock signal from the voltage-controlled oscillator is varied and it takes time to obtain the normal phase synchronization even when the read data are normally provided again after the read data losing period has passed. Therefore, the synchronizing operation is performed again in a state in which the input data are lost, i.e., a bit slip is caused so that all the subsequent data are read in error.